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Publications

Publications

List of Selected Publications

Journals

  1. Kanika Monga, Nitin Chaturvedi, S. Gurunarayanan, " Design of a STT-MTJ based Random-Access Memory with In-situ Processing for Data-Intensive Applications," in IEEE Transactions on Nanotechnology, Vol:21, pp.455-465, 17 Aug 2022. doi: 10.1109/TNANO.2022.3199230. (SCI Indexed).

  2. A. Dixit, N. Gupta and N. Chaturvedi, "Ab Initio Study of Carbon Nanotube Field Effect Transistor Gas Sensor for Detection of Ammonia and Nitrogen dioxide Gas," in IEEE Transactions on Nanotechnology, doi: 10.1109/TNANO.2022.3192015. (SCI Indexed)

  3. K. S. Beegam, M. V. Shenoy and N. Chaturvedi, "Hybrid Consensus and Recovery Block-Based Detection of Ripe Coffee Cherry Bunches Using RGB-D Sensor," in IEEE Sensors Journal, vol. 22, no. 1, pp. 732-740, 1 Jan.1, 2022, doi: 10.1109/JSEN.2021.3130747. (SCIE Indexed)

  4. Nidhi Chaturvedi, Rajdeep Chowdhury, Shivanshu Mishra, Kuldip Singh, Nitin Chaturvedi, Ashok Chauhan, Surojit Pande, Niketa Sharma, Priyavart Parjapat, Ramakant Sharma, “GaN HEMT based biosensor for the detection of breast cancer marker (C-erbB2)”, Semiconductor Science and Technology, Volume 36, Number 4, 2021. (SCIE Indexed)

  5. Kanika Monga, Kunal Harbhajanka, Arush Srivastava, Nitin Chaturvedi, S. Gurunarayanan “Design of an MTJ/CMOS based Asynchronous System for Ultra-Low Power Energy Autonomous Applications” Journal of Circuits, Systems and Computers. World Scientific, Volume 30, Issue 4, 2021. (SCIE Indexed)

  6. K. Monga, N. Chaturvedi and S. Gurunarayanan, "A Dual-Mode In-Memory Computing Unit Using Spin Hall-Assisted MRAM for Data-Intensive Applications," in IEEE Transactions on Magnetics, vol. 57, no. 4, pp. 1-10, April 2021. (SCIE Indexed)

  7. N. Sharma, C. Periasamy, N. Chaturvedi, N. Chaturvedi, “Trapping Effects on Leakage and Current Collapse in AlGaN/GaN HEMTs”, Journal of Electronic Material, Volume 49, pp. 5687–5697, 2020. (SCI Indexed)

  8. Kanika Monga, Nitin Chaturvedi and S. Gurunarayanan, "Energy-efficient data retention in D flip-flops using STT-MTJ", Circuit World, Emerald Insight, Volume 46, Issue 4, pp. 229-241, 2020, doi: 10.1108/CW-09-2018-0073. (SCIE Indexed)

  9. Kanika Monga, Nitin Chaturvedi and S. Gurunarayanan, “Design of a novel CMOS/MTJ-based multibit SRAM cell with low store energy for IoT applications”, International Journal of Electronics, Taylor & Francis, Volume 107, Issue 6, pp. 899-914, 2020. (SCI Indexed)

  10. Niketa Sharma, Shivanshu Mishra, Kuldip Singh, Nitin Chaturvedi, Ashok Chauhan, C. Periasamy, Dheeraj Kumar Kharbanda, Priyavart Parjapat, P. K. Khanna, and Nidhi Chaturvedi, "High-Resolution AlGaN/GaN HEMT-Based Electrochemical Sensor for Biomedical Applications," in IEEE Transactions on Electron Devices, vol. 67, no. 1, pp. 289-295, Jan. 2020. (SCI Indexed)

  11. Smita Pareek, Nitin Chaturvedi, Ratna Dahiya, “Optimal interconnections to address partial shading losses in solar photovoltaic arrays”, Solar Energy, Volume 155, pp 537-551, 2017. (SCIE Indexed)

  12. Nitin Chaturvedi, S. Gurunarayanan, “An efficient adaptive block pinning for multicore architectures”’ Microprocessors and Microsystems, Volume 39, Issue 3, pp 181-188, 2015. (SCI Indexed)

  13. Nitin Chaturvedi, A. Subramaniyan, & S. Gurunarayanan, “An adaptive migration–replication scheme (AMR) for shared cache in chip multiprocessors”, Journal of Supercomputing, Vol. 71, pp 3904–3933, 2015. (SCI Indexed)

  14. Nitin Chaturvedi, S Gurunarayanan, “An Efficient Data Access Policy in shared Last Level Cache”, WSEAS TRANSACTIONS on COMPUTER, Vol 14, 2015.

  15. Nitin Chaturvedi, Arun Subramaniyan, S. Gurunarayanan, “Selective Cache Line Replication Scheme in Shared Last Level Cache”, Procedia Computer Science, Volume 46, pp 1095-1107, 2015. (SCOPUS Indexed)

  16. L.Gautam, N. Chaturvedi, A Gupta, “Development of micronutrients rich homemade extruded food products with the incorporation of processed foxtail millet, wheat and chickpea” Indian Journal of Community Health (IJCH), Vol 26, 2014. (SCOPUS Indexed)

  17. Nitin Chaturvedi, S Gurunarayanan, “STUDY OF VARIOUS FACTORS AFFECTING PERFORMANCE OF MULTI-CORE PROCESSORS”, International Journal of Distributed and Parallel Systems (IJDPS) Vol.4, No.4, July 2013.

  18. Nitin Chaturvedi, Jithin P Thomas, S Gurunarayanan, “Adaptive Zone-Aware Multi-bank on Chip Last Level L2 Cache Partitioning for Chip Multiprocessors” International Journal of Computer Applications, Volume 7– No.1, September 2010.

  19. Nitin Chaturvedi, Jithin Thomas, S Gurunarayanan, “ADAPTIVE BLOCK PINNING BASED: DYNAMIC CACHE PARTITIONING FOR MULTI-CORE ARCHITECTURES”, International Journal of Computer Science & Information Technology (IJCSIT), Vol 2, No 6, December 2010.



Conferences

  1. K. Monga, S. Aggarwal, N. Chaturvedi and S. Gurunarayanan, "A Novel Decoder Design for Logic Computation in SRAM: CiM-SRAM," 2021 IEEE 18th India Council International Conference (INDICON), 2021, pp. 1-4, 2021.

  2. T. Alladi, V. Venkatesh, V. Chamola and N. Chaturvedi, "Drone-MAP: A Novel Authentication Scheme for Drone-Assisted 5G Networks," IEEE INFOCOM 2021 - IEEE Conference on Computer Communications Workshops (INFOCOM WKSHPS), 2021.

  3. K. Monga, N. Chaturvedi and S. Gurunarayanan, "Design of a Low Power Approximate Adder based on Magnetic Tunnel Junction for Image Processing Applications," 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2021.

  4. R. R. Thakur, N. Chaturvedi, N. Chaturvedi, “Off-State Leakage Concern in Scaling Nanowire FETs”, Innovations in Electrical and Electronic Engineering, Lecture Notes in Electrical Engineering, vol 756. Springer, Singapore, 2021.

  5. R. R. Thakur, M. P. Singh, N. Chaturvedi and N. Chaturvedi, "Performance Analysis of GaN and ZnO Gate All Around Nanowire FET at sub-5nm Technology," 2020 5th IEEE International Conference on Emerging Electronics (ICEE), 2020.

  6. K. Monga, N. Chaturvedi and S. Gurunarayanan, "Design of a Low Power 11T-1MTJ Non-Volatile SRAM Cell with Half-Select Free Operation," 2020 IEEE 17th India Council International Conference (INDICON), 2020.

  7. K. Monga, L. Maheshwari, N. Chaturvedi and S. Gurunarayanan, "Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array," 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020.

  8. R. R. Thakur, M. P. Singh, N. Chaturvedi and N. Chaturvedi, "Performance Analysis of GaN and ZnO Gate All Around Nanowire FET at sub-5nm Technology," 2020 5th IEEE International Conference on Emerging Electronics (ICEE), 2020.

  9. K. Monga, N. Chaturvedi and S. Gurunarayanan, "Design of a Robust Logic Gate using Magnetic Tunnel Junction," 2019 IEEE 16th India Council International Conference (INDICON), 2019.

  10. K. Monga, A. Malhotra, N. Chaturvedi and S. Gurunayaranan, "A Novel Low Power Non-Volatile SRAM Cell with Self Write Termination," 2019 10th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2019.

  11. Mudit Chandaliya, Nitin Chaturvedi and S Gurunarayanan, “An exploration of neuromorphic systems and related design issues/challenges in dark silicon era” 331, 3rd International Conference on Communication Systems (ICCS-2017) 14–16 October 2017.

  12. Nikesh Sharma, Smita Pareek, Nitin Chaturvedi and Ratna Dahiya, “Multiple Solutions for Reconfiguration to Address Partial Shading Losses in Solar Photovoltaic Arrays, 3rd International Conference on Communication Systems (ICCS-2017), Volume 331, 14–16 October 2017.

  13. D. Suneja, N. Chaturvedi and S. Gurunarayanan, "A comparative analysis of read/write assist techniques on performance & margin in 6T SRAM cell design," 2017 International Conference on Computer, Communications and Electronics (Comptelix), 2017.

  14. S. Jain, N. Chaturvedi and S. Gurunarayanan, "Design and analysis of 6T SRAM cell with NBL write assist technique using FinFET," 2017 International Conference on Computer, Communications and Electronics (Comptelix), 2017.

  15. N. Bhimsaria, N. Chaturvedi and S. Gurunarayanan, "Design of non-volatile asynchronous circuit using CMOS-FDSOI/FinFET technologies," 2016 International Conference on Computing, Analytics and Security Trends (CAST), 2016.

  16. P. Kalra, S. Hussain and N. Chaturvedi, "An Investigation of Power-Performance Aware Accelerator/Core Allocation Challenges in Dark Silicon Heterogeneous Systems," 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 2016, pp. 52-55, doi: 10.1109/iNIS.2016.023.

  17. N. Chaturvedi and S. Gurunarayanan, "An Adaptive Block Pinning Cache for Reducing Network Traffic in Multi-core Architectures," 2013 5th International Conference and Computational Intelligence and Communication Networks, 2013.

  18. N. Chaturvedi, P. Sharma and S. Gurunarayanan, "An adaptive coherence protocol with adaptive cache for multi-core architectures," 2013 International Conference on Advanced Electronic Systems (ICAES), 2013, pp. 197-201, doi: 10.1109/ICAES.2013.6659391.

  19. Mittal, S and Makwana, I and N. Chaturvedi, and Chaturvedi, N, “Role of Sensing Parameters in Breast Cancer Detection using GaN HEMTs”, International Conference on Emerging Technologies: Micro to Nano (ETMN - 2013), February 23-24, 2013.

  20. Sharma, N and Joshi, D and N. Chaturvedi, and N. Chaturvedi, “Recess Dependent AlGaN/GaN HEMTs Performance” International Conference on Emerging Technologies: Micro to Nano (ETMN - 2013), February 23-24, 2013.

  21. J. P. Thomas, K. R. S. N. Kumar, V. Addanki, A. Gupta and N. Chaturvedi, "Hardware Implementation of a Biometric Fingerprint Identification System with Embedded Matlab," 2010 International Conference on Advances in Recent Technologies in Communication and Computing, 2010.

  22. M. Menon, K. Dhall, A. Gupta and N. Chaturvedi, "Low Power Cascaded Three Stage Amplifier with Multipath Nested Miller Compensation," 2010 International Conference on Recent Trends in Information, Telecommunication and Computing, 2010.

  23. M. Menon, K. Dhall, A. Gupta and N. Chaturvedi, "Low Power Cascaded Three Stage Amplifier with Multipath Nested Miller Compensation," 2010 International Conference on Recent Trends in Information, Telecommunication and Computing, 2010.

  24. V. Gupta, A. Gupta, N. Chaturvedi and A. Asati, "A Novel Technique for Improvement of Power Supply Rejection Ratio in Amplifer Circuits," 2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies, 2009.



Book Chapters

  1. Gautham Sundar Ram, R., Chaturvedi, N., Saurav, S., Singh, S. (2020). An FPGA Based Hardware Accelerator for Classification of Handwritten Digits. In: Abraham, A., Cherukuri, A., Melin, P., Gandhi, N. (eds) Intelligent Systems Design and Applications. ISDA 2018 2018. Advances in Intelligent Systems and Computing, vol 940. Springer.

  2. Monga, K., Chaturvedi, N. (2019). A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF Applications. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore

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