SYNOPSIS
NAME: ANU GUPTA
ID. NO.: 1995PHXF405
TITLE: DESIGN EXPLORATIONS OF VLSI ARITHMETIC CIRCUITS
Adders of various bit-widths are frequently required in very large-scale integrated circuits (VLSI) from processors to application specific integrated circuits (ASICs). Addition is one of the fundamental arithmetic operations. Adders are essential not only for addition, but also for subtraction, multiplication, and division. The most important and widely accepted metrics for measuring the quality of adder designs in the past were propagation delay, and area. Efforts in the past were focused towards increasing the speed of computing systems. Reducing power consumption has gained importance more recently - both because of increasing levels of integration and the desire for portability. There is an increasing demand for portable applications requiring high throughput and vastly increased capabilities like notebook, laptop computers and personal communication services (PCS’s) without the need to be connected to a wired network.
Though improvements in battery technology are being made, the progress there is slow as compared to the advances in electronic circuits and it is unlikely to provide a solution to the power problem. [Powers 1995] It has thus become imperative to develop integrated circuits and systems that use less energy-without greatly sacrificing computational throughput. The situation has been further aggravated by the fact that microprocessor on-chip clock rates have already crossed 1 GHz mark, leading to a substantial increase in dynamic (switching) power consumption. Furthermore energy efficient circuits are also needed in high performance desktops, AC powered systems in which sinking large amount of heat through packages is becoming a difficult problem. Thus designing a low-power processor is as important as designing a high performance one.
Despite the simplicity of addition, there isn’t a single best way to perform high-speed addition. [Hennessy et al. 1996] The adder architectures are available from the simple but slow ripple carry adder to the fairly complex but fast carry look-ahead adder. The performance of adders also depends upon the choice of logic design style and the transistor sizes used. Hence there exist numerous possibilities of making changes in the adder designs because of which many designs can be developed and the performance of every design will differ from other designs.
The objective of this thesis is to explore the design space of VLSI adders of different bit-widths in terms of their architectures, logic design styles, transistor sizes, and layout design styles with a view to understand the contributions to speed, energy consumption and area that come from each of these factors so that a design-advisor tool can be built to automatically select an optimal adder configuration based on the constraints of speed and energy consumption per addition.
Five adder architectures have been chosen that are frequently used in arithmetic circuits i.e. ripple carry adder, carry skip adder, carry select adder, conditional sum adder, and carry look-ahead adder for operand sizes of 4, 8, 16, 32, and 64 bits. We have used four circuit design styles: fully static CMOS, domino CMOS, dual pass transistor logic and complementary pass transistor logic and gates with 2 to 4 inputs, for designing adders. Also, each adder architecture has been designed using three different transistor sizes - (w/l) =1.5, 3, and 5 for a particular logic design style.
Standard cell approach has been chosen to create the designs of different adders. Standard cells of basic logic blocks have been designed in different logic design styles. The technology used is a 1.2μm N-well CMOS technology. Also, three versions of each cell have been created for three different transistor sizes keeping channel length the same and varying only the channel widths. The adders circuits have been designed using Tanner Tools and the library of schematic symbols corresponding to the standard cells are generated using schematic editor S-Edit. The layouts have been generated using automatic placement and routing tool ‘SPR’ of Tanner Tool’s layout editor L-Edit. The extracted netlists of the adder designs were simulated to generate the values of worst-case propagation delay and energy consumption per addition.
Simulation results show that -
Ø Energy consumption per addition increases and worst-case propagation delay decreases with increase in transistor size.
Ø Fully static CMOS logic design style is the most energy efficient design style for all architectures except for conditional sum adder architecture, which consumes least energy per addition for CPL design style.
Ø Ripple carry adder architecture consumes least energy per addition in comparison to other architectures for all logic design styles.
Ø For 4-bit, 8-bit and 16-bit operand sizes, conditional sum adder architecture designed in CPL design style results in highest-speed addition. For 32-bit and 64-bit operand sizes, carry look-ahead adder architecture designed in fully static CMOS logic gives the fastest addition.
Ø Carry look-ahead adder architecture is faster than other architectures for fully static CMOS, and domino CMOS logic design styles.
Ø Performance of adder architectures varies with operand size. For 4-bit operand size, ripple carry adder architecture has the least energy-delay product (EDP) irrespective of logic design style and transistor size except in domino CMOS logic where carry look-ahead adder shows nearly the same value but with higher transistor count. For 16-bit and larger operand sizes - carry look-ahead adder architecture has the least EDP for fully static CMOS and domino CMOS logic design styles whereas conditional sum adder architecture has the smallest EDP for pass transistor logic design styles. For 8-bit operand size, carry look-ahead architecture for fully static CMOS and conditional sum architecture for other logic design styles have the least EDP.
Ø Ripple carry architecture has the smallest transistor count and core area for all logic design styles. CPL design style based adders have the smallest transistor count for all architectures. Domino CMOS logic design style has a higher transistor count than fully static CMOS logic design style because standard cells having only 2 to 4 inputs have been used in designs.
From the above results, it is observed that ripple carry adder architecture designed using fully static logic design style is most suitable for low-energy applications. Carry look-ahead architecture is most suitable for high-speed operation for larger operand sizes. In pass transistor logic; CPL is better than DPL, both, in terms of energy consumption and worst-case propagation delay due to less parasitic capacitances.
Energy-delay product (EDP) has been used as a basis for choosing an optimized adder design. The EDP has been found to vary with logic design style, and adder architecture. For fully static CMOS, and domino CMOS logic design styles, carry look-ahead adder architecture has the lowest EDP, and for pass transistor logic design styles, conditional sum architecture has the lowest EDP followed by carry look-ahead architecture. The EDPs obtained from simulation results of adders exhibit a smaller value at transistor width equal to 3.6μm (0.6 to 0.99 times the EDP of an adder obtained at transistor width equal to 1.8μm). This is because a moderate increase in (w/l) of the transistors used causes a more significant reduction in delay than the increase in energy consumed. This trend is observed in all adder designs for operand size of 64-bit (in some cases for smaller operand sizes also). Further increase in channel-width leads to an increase in EDP, as reduction in delay decreases whereas energy consumption keeps on increasing. Thus, the EDP of an adder shows a minimum at the channel width that is twice the minimum allowed channel width value.
We have studied the effect of layout methodology on EDP by comparing standard-cell based design and full-custom design of 64-bit ripple carry adder and carry look-ahead adder in fully static CMOS logic design style. Full custom layouts of the full-adder cell, the A-cell and B-cell of carry look-ahead adder have been drawn which were then used in creating designs of 64-bit ripple carry and carry look-ahead adders. The EDP of full custom designs is found to be much less than the EDP of standard cell based designs due to significant decrease in parasitic capacitances. But, in full custom designs too, the EDP has been found to be minimum for (w/l)=3 and increases with further increase in (w/l). Hence, the adders designed with full-custom layout methodology also give an optimum value for channel width (w) twice the minimum allowed value.
In the present work, energy analysis has been done using energy consumption per addition for an input combination corresponding to the worst-case propagation delay. Since the power dissipation in combinational circuits is pattern dependent, we have also, obtained the average energy consumption per addition for a set of randomly generated input vectors for 4-bit adder designs. Results show that the energy consumption per addition for a set of randomly applied input vectors is nearly a constant multiple of the energy consumption per addition for worst-case propagation delay input pattern for a given logic design style. Hence, the grading of different adder architectures in terms of their energy consumption applies to the case of randomly applied input vectors also.
For modeling the worst-case propagation delay, the approach of identifying the critical delay paths of adders is used. The product of number of gates in critical delay path, time constant of the technology (τ), average fan-out per gate in critical delay path (f), and the parasitic degradation factor (α) has been used to estimate the worst-case propagation delay. The time constant (τ) has been obtained for different transistor sizes without including the circuit parasitics using SPICE. The parasitic degradation factor (α) of all adder designs is obtained empirically by equating the delay value obtained from simulation to this product. The variation of (α) with operand size is obtained for all adders designed using different circuit design styles and a second order polynomial is fitted to the data. Thus equations linking (α) to operand size are obtained which have been used for determining (α) of an adder of any size between 4 to 64-bit. This value is then used in the product for estimating the worst-case propagation delay.
For modeling the energy consumption per addition, product of average energy consumption (E) in driving 1Cg load, average number of nodes (ns) undergoing transitions for all possible transitions from an input pattern to another input pattern, glitch factor (g), average weight factor (Ψ) per gate, average load capacitance at the output of a gate (χ), and the parasitic degradation factor (α) is taken. Energy consumption (E) in driving one gate capacitance has been obtained through SPICE simulation without including circuit parasitics and (χ) has been calculated from adder schematics. The value of (g) is taken as 1.5 for static logic and 1 for dynamic logic. Average weight factor (Ψ) has been estimated by taking average of weight factors of different gates used in the design for a particular logic design style. Worst-case propagation delay values have been obtained from: (1) delay model, (2) through quadratic fits to available data points and, (3) actual SPICE simulation. Results show a close match between the values.
Energy consumption per addition for worst-case propagation delay input combination has been obtained through SPICE simulation, and (2) through quadratic fits to available data points. The results show a close match between the values. Energy model correctly grades the adder designs for their energy consumption - but the estimates of energy consumption it provides are slightly different from those provided by simulation due to the fact that in our modeling we have considered an average value of weight-factor for all the gates used in the design using a particular logic design style that accounts for energy consumption in switching of nodes internal to a gate.
Based on all the explorations and modeling work described above, we have developed a tool that can automatically suggest the optimal architecture, logic design style, and the transistor size for a given specification of operand size, speed and energy consumption per addition. This tool thus helps the designer in quickly selecting the best-suited adder design for his requirement.