Publications

Patent, Projects, Journals, Conferences and talks

Published Indian Patent:

[1]Prateek Sikka,Abhijit Asati, Chandra Shekhar

"A method of high level synthesis in integrated circuit design using application specific bit widths"

IN Patent App.number: 201911028124 (Applied in July, 2019, Published in January 2021)

https://ipindia.gov.in/writereaddata/Portal/IPOJournal/1_4943_1/Part-1.pdf

(First Examination Report (FER) received and response submitted.)

Project Completed/On-going:

(4) 2022-2025 : (On-going)

Topic: Convolutional neural networks and their Hardware Implementation for Improved Performance.

Amount: INR 21,81,825/-

Sponsored by DST, New Delhi.

Role: Mentor of DST

Status: Ongoing

(3) 26^th May to 5^th July 2014: (Completed)

Topic: RTL to GSDII flow and DFT implementation

Cypress Semiconductor Ltd. Bangalore

Amount: 44944.01/-

(2) April, 2004:(Completed)

Topic: Unsigned binary division circuit using non-restoring division method

Project contest of Curriculum Development Program jointly organized by INTEL Higher Education and IIT Bombay

(1)Aug-Dec 2002: (Completed)

M.E. Thesis project on “Design of Application Specific Processor for text to speech-conversion for Indian Languages” at Central Electronics Engineering Research Institute, Pilani.

Journals

[40] Jyoti Pandey, Abhijit R. Asati, "Lightweight convolutional neural network architecture implementation using TensorFlow lite," Springer's International Journal of Information Technology (DOI:https://doi.org/10.1007/s41870-023-01320-9) Scopus Indexed, Impact factor:2.51 (June 2023)

(Link: https://universe.bits-pilani.ac.in/microadmin/login.aspx )

[39] Prateek Sikka, Abhijit R Asati, Chandra Shekhar, "Area, Speed and Power Optimized Implementation of a Band-pass FIR Filter Using High-Level Synthesis", Springer Journal of Wireless Personal Communications, Electronic ISSN:1572-834X, Print ISSN:0929-6212, https://doi.org/10.1007/s11277-021-08727-2, July 2021. Impact Factor: 1.954, SNIP: 0.789, SCI Indexed, WOS and Scopus Indexed

(Link: https://link.springer.com/article/10.1007/s11277-021-08727-2 )

[38] Prateek Sikka, Abhijit R Asati, Chandra Shekhar, " Real-time FPGA Implementation of a High-Speed and Area-Optimized Harris Corner Detection Algorithm," Elsevier Microprocessors and Microsystems, DOI: https://doi.org/10.1016/j.micpro.2020.103514, Vol. 80, February 2021, Impact Factor: 1.53, SNIP: 1.197, SCI Indexed, WOS and Scopus Indexed

(Link: https://www.sciencedirect.com/science/article/pii/S0141933120306645 )

[37] Prateek Sikka, Abhijit R Asati, Chandra Shekhar, "Power and Area Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications" Springer Journal of Circuits, Systems, and Signal Processing, https://doi.org/10.1007/s00034-020-01601-9 , November 2020, Impact Factor: 2.23, SNIP:0.862, SCI Indexed, WOS, ACM Digital Library and and Scopus Indexed

(Link: https://link.springer.com/article/10.1007/s00034-020-01601-9)

[36] Vineet Kumar, Abhijit Asati, and Anu Gupta, “Dedicated Hardware Architecture for Localizing Iris in VW Images,” Elsevier Journal of King Saud University - Computer and Information Sciences, https://doi.org/10.1016/j.jksuci.2020.11.004, Nov. 2020, Impact Factor:13.473 SNIP: 2.795, ESCI and Scopus Indexed, )

(Link: https://www.sciencedirect.com/science/article/pii/S1319157820305292 )

[35] Prateek Sikka, Abhijit R Asati, Chandra Shekhar, "Speed Optimal FPGA Implementation of the Encryption Algorithms for Telecom Applications," Elsevier Microprocessors and Microsystems DOI: https://doi.org/10.1016/j.micpro.2020.103324, Vol. 79, November 2020, Impact Factor: 1.53, SNIP:1.197, SCI Indexed, WOS and Scopus Indexed

(Link: https://www.sciencedirect.com/science/article/pii/S014193312030483X )

[34] Prateek Sikka, Abhijit R Asati, Chandra Shekhar, "High-Level Synthesis Assisted Design and Verification Framework for Automotive Radar Processors," Elsevier Microprocessors and Microsystems, DOI: https://doi.org/10.1016/j.micpro.2020.103259, Vol. 78, October 2020, Impact Factor: 1.53, SNIP:1.197 SCI Indexed, WOS and Scopus Indexed

(Link: https://www.sciencedirect.com/science/article/pii/S0141933120304191)

[33] Prateek Sikka, Abhijit R Asati and Chandra Shekhar, "High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications," Springer Journal of Ambient Intelligence and Humanized Computing, 29 July, 2020, DOI: 10.1007/s12652-020-02403-2, ISSN: 18685145, 18685137 (Rtr.) -- Impact Factor: 7.10, SNIP:2.085, SCI Expanded Indexed (SCIE), WOS and Scopus indexed

(Link: https://link.springer.com/article/10.1007/s12652-020-02403-2)

[32] Prateek Sikka, Abhijit Asati, Chandra Shekhar, "High‐speed and area‐efficient Sobel edge detector on field programmable gate array for artificial intelligence and machine learning applications" International journal of Computational Intelligence, Wiley Periodicals LLC, April 2020, DOI: 10.1111/coin.12334, ISSN: 0824-7935, E-ISSN:1467-8640, - Impact Factor: 2.33, SNIP:1.025, SCI Expanded Indexed (SCIE), WOS and Scopus Indexed

(Link: https://onlinelibrary.wiley.com/doi/full/10.1111/coin.12334)

[31] Vanya Gupta, Garima Singh, Abhijit Asati, "BIST Architecture for Combinational Circuit," International Journal of Electrical, Electronics and Data Communication (IJEEDC), Volume-7, Issue-5, May-2019 eISSN:2320-2084 , pISSN:2321-2950 (Publons, Academic Journals database, Index Copernicus)

(Link: http://ijeedc.iraj.in/paper_detail.php?paper_id=15458)

[30] Vineet Kumar, Abhijit Asati and Anu Gupta, “ Memory-Efficient Architecture of Circle Hough Transform and Its FPGA Implementation for Iris Localization,” IET Image Processing, Volume 12, Issue 10, pp. 1753 – 1761, October 2018. DOI: 10.1049/iet-ipr.2017.1167 , Print ISSN 1751-9659, Online ISSN 1751-9667 -- Impact factor: 2.37, SNIP: 1.167, SCI Indexed, WOS and Scopus Indexed

(Link: https://ieeexplore.ieee.org/document/8467468)

[29] Anu Gupta Priya Gupta, and Abhijit Asati; "Novel Low Power and Stable SRAM Cells for Subthreshold operation at 45 nm" Taylor & Francis, International Journal of Electronics, Vol. 105, No. 8, February 2018. (DOI:10.1080/00207217.2018.1440437) --Impact factor: 1.34, SNIP:0.737, SCI, SCI Expanded Indexed (SCIE), WOS and Scopus Indexed

(Link: https://www.tandfonline.com/doi/full/10.1080/00207217.2018.1440437)

[28] Vineet Kumar, Abhijit Asati, Anu Gupta, “Hardware Accelerators for Iris Localization”, Springer Journal of Signal Processing Systems, September 2017. ( DOI: 10.1007/s11265-017-1282-2) -- Impact factor:1.35, SNIP: 0.681, SCI Expanded Indexed (SCIE), WOS and Scopus Indexed

(Link: https://link.springer.com/article/10.1007/s11265-017-1282-2

https://dl.acm.org/doi/10.1007/s11265-017-1282-2)

[27] Vineet Kumar, Abhijit Asati and Anu Gupta,"Low-Latency Median Filter Core for Hardware Implementation of 5-by-5 Median Filtering," IET Image Processing, August 2017, (DOI: 10.1049/iet-ipr.2016.0737, --Impact Factor: 2.37, SNIP: 1.167, SCI Indexed, WOS and Scopus Indexed

(Link: https://ieeexplore.ieee.org/document/8068794)

[26] Ashish Mishra, Mohit Agarwal, Abhijit Asati and Kota Solomon Raju "Using graph isomorphism for mapping of data flow applications on reconfigurable computing systems," Elsevier Microprocessors and Microsystems, December 2016.(DOI: 10.1016/j.micpro.2016.12.008) -- Impact Factor: 1.53, SNIP:1.197,SCI Indexed, WOS and Scopus Indexed

(Link: https://www.sciencedirect.com/science/article/pii/S0141933116304239)

[25] Abhinav Bhansali, Abhijit Asati^{, ”}Optimizing the ratio of number of tubes in PCNTFET to NCNTFET for digital circuits”Journal of Microelectronics and Solid State Devices, Vol. 5, No.1. 2018, ISSN: 2455-3336 (DOI: https://doi.org/10.37591/jomsd.v5i1.650) -- Index Copernicus, DRJI, UGC listed.

(Link: http://engineeringjournals.stmjournals.in/index.php/JoMSD/article/view/650)

[24]Priya Gupta, Anu Gupta, Abhijit Asati, "Leakage Immune 9T-SRAM Cell in Sub-threshold Region," Bulletin of Electrical Engineering and Informatics, Vol 5, 2016 (DOI: 10.11591/eei.v5i1.557) --SJR: 0.44, SNIP:0.954, Scopus Indexed

(Link: https://doi.org/10.11591/eei.v5i1.557 )

[23] Priya Gupta, Ishan Munje, Anu Gupta and Abhijit Asati, "Effectiveness of body bias and hybrid logic: an energy efficient approach to design adders in sub-threshold regime," International Journal of Circuits and Architecture Design (Inderscience Publishers),Vol. 2 No. 2, 2016. (DOI: 10.1504/IJCAD.2016.10003038) -- CNPIEC Indexing

(Link: https://www.inderscience.com/offer.php?id=82137)

(Link: https://www.inderscienceonline.com/doi/abs/10.1504/IJCAD.2016.082137 )

[22]Vineet Kumar, Abhijit Asati and Anu Gupta, "Hardware implementation of a novel edge-map generation technique for pupil detection in NIR Images," Elsevier Journal Engineering Science and Technology, an International Journal (JESTEC), November 2016, (DOI: 10.1016/j.jestch.2016.11.001) -- Impact Factor:4.360, SNIP: 2.432, Scopus Indexed, SCI, WOS and Scopus Indexed

(Link: https://www.sciencedirect.com/science/article/pii/S2215098616305456)

[21]Vineet Kumar, Abhijit Asati and Anu Gupta, “Accurate iris localization using edge map generation and adaptive circular Hough transform for less constrained infrared iris images,” International Journal of Electrical and Computer Engineering, IAES publication, Indonesia, Vol. 6, No.4, pp. 1637-1646, August 2016. DOI: http://doi.org/10.11591/ijece.v6i4.pp1637-1646, (ISSN:1693-69308) --SNIP: 1.090, H index: 8, Scopus Indexed

(Link: http://ijece.iaescore.com/index.php/IJECE/article/view/732)

[20] Vineet Kumar, Abhijit Asati and Anu Gupta, “A novel edge-map creation approach for highly accurate pupil localization in unconstrained infrared iris images”, Journal of Electrical and Computer Engineering, Hindavi publishing corporation Vol. 2016, Article ID 4709876, May 2016. (DOI:10.1155/2016/4709876) --H index:20, SNIP: 0.926, Emerging Source Citation Index (ESCI), WOS and Scopus Indexed

(Link: https://www.hindawi.com/journals/jece/2016/4709876/)

[19] Mishra Ashish, Sharma Aditya, Verma Pranet, Abhijit Asati and Raju Kota Solomon " A modular approach to random task graph generation," Journal of Science and Technology, Volume 9, Issue 8, February 2016 (link: http://www.indjst.org/index.php/indjst/article/view/61035), Print ISSN : 0974-6846, Online ISSN : 0974-5645 -- IC Impact Factor: 5.07, SNIP: 1.270, Scopus Indexed

(Link: https://indjst.org/articles/a-modular-approach-to-random-task-graph-generation)

[18] Priya Gupta, Anu Gupta and Abhijit Asati, “ Ultra low power MUX based compressors for Wallace and Dadda multipliers in sub-threshold regime,” American Journal of Engineering and Applied Sciences, Vol. 8, Issue 4, pp:702-716, Nov. 2015. (DOI:10.3844/ajeassp.2015.702.716) --RG Impact 3.52, Impact Factor: 0.545, SCImago Indexed, SNIP: 0.693, Scopus Indexed

(Link: https://thescipub.com/abstract/10.3844/ajeassp.2015.702.716)

[17] Priya Gupta, Anu Gupta and Abhijit Asati, "Leakage Immune Modified Pass Transistor based 8T-SRAM Cell in Sub-threshold Region," International Journal of Reconfigurable Computing Hindavi publishing corporation Volume 2015. (DOI:10.1155/2015/749816) -- H Index: 13, SNIP: 0.691, Scopus Indexed, WOS, Emerging Source Citation Index (ESCI) and Scopus Indexed

(Link: https://www.hindawi.com/journals/ijrc/2015/749816/)

[16] Ashish Mishra, Vivek Vanga, Vani V, Abhijit Asati and Kota Solomon Raju, "Resource estimation of programs for reconfigurable computing systems," International Journal of Applied Engineering Research (IJAER), Volume 10, Number 12, pp. 30699-30712, 2015. (Print ISSN: 0973-4562, Online ISSN: 0973-9769) --H index:25, SNIP: 0.484, Scopus Indexed

(Link: https://www.ripublication.com/Volume/ijaerv10n12.htm)

[15] Priya Gupta, Anu Gupta and Abhijit Asati "Power-aware design of logarithmic prefix adders in subthreshold regime: A comparative analysis," Elsevier journal of Procedia Computer Science, Vol. 46, pp. 1401 – 1408, https://doi.org/10.1016/j.procs.2015.02.058, H index:47, SNIP: 1.035, WOS and Scopus Indexed

015. (ISSN: 1877-0509) --

(Link: https://www.sciencedirect.com/science/article/pii/S1877050915001222)

[14] A. Mishra, R. Jimit, Abhijit Asati, K.S. Raju, " Mapping and partitioning of task graphs using Kernighan-Lin/Fiduccia-Mattheyses algorithm,” International Journal of Emerging Technologies in Computational and Applied Sciences (IJETCAS), Issue 11, Vol. 1, pp. 58-61, Feb., 2015. (ISSN: 2279-0047) --IBI Factor:3.1, SSRN, Microsoft Academic Search, INSPEC, Mendeley, ResearchGate and others

(Link: http://iasir.net/ijetcasissue/ijetcasissue11-1.html)

(Link: http://iasir.net/IJETCASpapers/IJETCAS15-130.pdf )

[13] Abhijit Asati," Logic design style based NBTI degradation study using Verilog," International Journal of Emerging Technologies in Computational and Applied Sciences (IJETCAS), Issue10 ,Volume 3, pp. 207-213, September-November, 2014, ISSN: 2279-0055 (Online) ISSN : 2279-0047 (Print) Index Copernicus, SSRN, Microsoft Academic Search, INSPEC, Mendeley, ResearchGate and others

(Link: http://iasir.net/ijetcasissue/ijetcasissue10-3.html)

(Link: http://iasir.net/IJETCASpapers/IJETCAS14-776.pdf )

[12] Priya Gupta, Anu Gupta and Abhijit Asati,"Design and implementation of N-bit sub-threshold Kogge Stone adder with improved power delay product," European Journal of Scientific Research, Volume 123, No 1, 106-116, June, 2014. (ISSN: 1450-216X/1450-202X) (Impact Factor: 0.713) -- Monitored by SCI, Indexed, H index:44

(Link https://www.europeanjournalofscientificresearch.com/issues/EJSR_123_1.html)

[11] Priya Gupta, Anu Gupta and Abhijit Asati “A Review on ultra low power design technique: sub-threshold logic,” International Journal of Computer Science and Technology-IJCST,Vol.4, Issue Spl-2, April-June 2013, ISSN: 0976-8491 (Online) ISSN : 2229-4333 (Print) -- DOAJ, Scribd

(Link: https://pdfs.semanticscholar.org/6ce8/f6ce093859ae78339e83d4ace1e5ebec7080.pdf)

[10] Bharat Kumar Potipireddi and Abhijit Asati, "Automated HDL Generation of two’s complement Dadda multiplier with parallel prefix adders," International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE), Vol. 2, Issue 6, June 2013. ISSN 2320 - 3765 (Print), ISSN 2278 – 8875 (Online). -- Index Copernicus, DRJI and other

(Link: https://www.ijareeie.com/upload/june/25B_AUTOMATED.pdf)

[9] Bharat Kumar Potipireddi and Abhijit Asati, "Automated HDL generation of two’s complement Wallace multiplier with parallel prefix adders," International Journal of Electronics and Communication Engineering & Technology (IJECET), Volume 4, Issue 3, May – June (2013). ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online). Index Copernicus, SSRN, Mendeley and other

(Link: https://www.semanticscholar.org/paper/AUTOMATED-HDL-GENERATION-OF-TWO%E2%80%99S-COMPLEMENT-WITH-Potipireddi-Asati/d656725046d17300fb5349ca2f99236f6161b3ee)

[8] Abhijit Asati and Chandra Shekhar, “Digital CMOS high-speed level shifter design, International Journal of Computers, Information Technology and Engineering, Vol.3, No. 1, Jan-June 2009 (ISSN: 0973-743X)

(Link: https://portal.issn.org/resource/ISSN/0973-743X )

(Link: https://www.scribd.com/document/73177709/1-Design-CMOS-Digital-Level-Shifter-Abhijit-Asati )

[7] Abhijit Asati and Chandra Shekhar, “ Sizing of pre-charge and pre-discharge transistors for domino logic design style, ” IETECH Journal of Communication Techniques, Vol. 3, No. 1, 2009. (ISSN: 0973-8053).

(Link: https://portal.issn.org/resource/ISSN/0973-8053/?language=ar)

[6] Abhijit Asati and Chandra Shekhar, “ Comparison of trans-conductance (ß) ratio for a high speed inverter design, ” ICFAI University Journal of Electrical & Electronics Engineering. Vol. II, No. 1, 2009. (ISSN 0974-1704) -- IUP Publication, Cabell's Directory, EBSCO/Proquest

(Link: https://www.iupindia.in/109/IJEEE_Trans-Conductance_Ratio_7.html)
[5] S. K. Sahoo, Anu Gupta, Abhijit Asati and Chandra Shekhar, "A novel redundant binary number to natural binary number converter,” Springer online Journal of Signal Processing System, June, 2009. ( DOI: 10.1007/s11265-017-1282-2) --Impact Factor: 1.35, SNIP: 0.681, SCI , WOS and Scopus Indexed

(Link: https://link.springer.com/article/10.1007/s11265-009-0392-x)
[4] S.K.Sahoo, Chandra Shekhar, Sudeepti Kodali Abhijit Asati and Anu Gupta, "Dual channel addition based FFT processor architecture for signal and image processing," International Journal of High Performance Systems Architecture, (Inderscience Publishers)

, Vol. 2, No. 1, 2009. (ISSN online: 1751-6536; ISSN print: 1751-6528DOI: 10.1504/IJHPSA.2011.038053) --Imapct Factor: 0.23, SNIP: 0.185, H index: 8, Scopus Indexed

(Link: https://www.inderscience.com/info/inarticle.php?artid=30097
https://dl.acm.org/doi/10.1504/IJHPSA.2009.030097 )
[3] Abhijit Asati and Chandra Shekhar, " A 16*16 MUX based multiplier design using optimized CMOS logic style" International Journal of Electronic Engineering Research, Vol. 1, No. 1, 2009. (ISSN 0975-6450 ) --ICI, Index Copernicus

(Link: https://www.ripublication.com/Volume/ijeerv1n1.htm)

Link: https://www.scribd.com/document/82294940/A-16A-16-MUX-Based-Multiplier-Design)

[2] Abhijit Asati and Chandra Shekhar, “ A high speed pipelined dynamic circuit implementation using modified TSPC logic design style with improved performance,” International Journal of Recent Trends in Engineering, Issue 1, Vol. 1, No.3, June 2009. [ISSN: 1797-9617]

(Link: https://www.semanticscholar.org/paper/A-High-Speed-Pipelined-Dynamic-Circuit-Using-TSPC-Asati/073ae23deb4c3dd601f143bd5689cb5d0c203c20)

(Link: http://search.proquest.com/openview/7910becee5e28e98e20093017143d385/1?pq-origsite=gscholarandcbl=136092 )

-- Leibniz Information Centre for Science and Technology Germany, Academy Publisher, Finland

[1] Abhijit Asati and Chandra Shekhar, "VLSI implementation of a high performance barrel shifter architecture using three different logic design styles," International Journal of Recent Trends in Engineering, Vol. 2, No. 7, November 2009. [ISSN: 1797-9617]

-- Leibniz Information Centre for Science and Technology Germany, Academy Publisher, Finland

(Link: https://www.semanticscholar.org/paper/Implementation-of-a-High-Performance-Barrel-Shifter-Asati-Chandrashekhar/182e61400713f8d 9ea865648b233133f948fe6e8)

Book Chapters

[3] Anu Gupta; Priya Gupta; Abhijit Asati, "Low-voltage, low-power SRAM circuits using subthreshold design technique"

IET Book VLSI and Post-CMOS Electronics. Design, modelling and simulation, (Editors: Rohit Dhiman; Rajeevan Chandel), Publication Year: 2019, (Book chapter 3, Book DOI: 10.1049/PBCS073F, Chapter DOI: 10.1049/ PBCS073F_ch3, ISBN: 9781839530524) Scopus Indexed

(Link: https://digital-library.theiet.org/content/books/10.1049/pbcs073f_ch3)

[2] Abhijit Asati, "High Performance CMOS Multiplier, Barrel Shifter and Modeling of NBTI" LAP LAMBERT Academic Publishing; 1 edition (31 August 2017) -- (ISBN-10: 6202025263, ISBN-13: 978-6202025263)

(Link: https://www.amazon.in/Performance-Multiplier-Barrel-Shifter-Modeling/dp/6202025263)

[1] Priya Gupta, Anu Gupta, Abhijit Asati contributed a chapter in a book titled "Handbook of research on advanced hybrid intelligent techniques and applications," IGI global Publisher, 2015. [Book chapter 4 (Detailed Analysis of Ultra Low Power Column Compression WALLACE and DADDA Multiplier in Sub-Threshold Regime) , ISBN13: 9781466694743, ISBN10: 1466694742, EISBN13: 9781466694750, DOI: 10.4018/978-1-4666-9474-3.ch004]

(Link: https://www.igi-global.com/chapter/detailed-analysis-of-ultra-low-power-column-compression-wallace-and-dadda-multiplier-in-sub-threshold-regime/140452)

International Conferences Abroad

[4] Vanya Gupta, Garima singh and Abhijit Asati, “BIST Architecture for Combinational Circuit,” 530th International Academic Conference on Engineering, Technology and Innovations (IACETI 2019), Phuket, Thailand on 6 -7 February 2019. -- Scopus Indexed

[3] Vineet Kumar, Abhijit Asati, Anu Gupta, “An Iris localization method for noisy infrared iris images" IEEE International Conference on Signal and Image Processing Applications (ICSIPA 2015) Kuala Lumpur, Malaysia, 18-21 October, 2015. -- WOS, Scopus Indexed (available on IEEE explore), H index: 7, SNIP:0.437

(Link: https://ieeexplore.ieee.org/document/7412191)

[2] Ankur Kumar and Abhijit Asati, "Iris based biometric identification system," International Conference on Audio,Language and Image Processing (ICALIP 2014), July 7-9, 2014 Sanghai, China. -- WOS, Scopus Indexed (available on IEEE explore) , H index: 7, SNIP:0.306

(Link: https://ieeexplore.ieee.org/document/7009797)

[1] Abhijit Asati and Chandra Shekhar, “A purely MUX based high speed barrel shifter VLSI implementation using three different logic design styles,” 3^rd International Asia Conference on Informatics in Control, Automation and Robotics (CAR 2011), Shenzhen, China, 24-25 December, 2011. --WOS and Scopus Indexed (Springer LNCS), H-index: 12

(Link: https://conference.researchbib.com/view/event/8454, https://link.springer.com/chapter/10.1007/978-3-642-27329-2_88)

Lecture Notes with conference name

[8] Shivam Singh, Prakash Kumar Ojha and Abhijit R. Asati, "Analysis of Logical Effort-Based Optimization in the Deep Submicron Technologies." In: Dhavse, R., Kumar, V., Monteleone, S. (eds) Emerging Technology Trends in Electronics, Communication and Networking. Lecture Notes in Electrical Engineering, vol 952. Springer, Singapore. (DOI: https://doi.org/10.1007/978-981-19-6737-5_3), pages 23-27, SNIP: 0.204, Scopus Indexed, December 2022.

Conference name: Fourth International Conference on Emerging Technology Trends in Electronics, Communication and Networking – ET2ECN 2021, 17-18, November, Sardar Vallabhbhai National Institute of Technology (SVNIT), Ichchhanath, Surat - 395007 Gujarat, INDIA, corresponding Author

Link: https://link.springer.com/chapter/10.1007/978-981-19-6737-5_3

[7] Saketh Ram, J.V.N., Jain, V.K., Asati, A. (2022). Adiabatic Logic Code Converter Design at Different Sub-micron Technologies. In: Pundir, A.K.S., Yadav, N., Sharma, H., Das, S. (eds) Recent Trends in Communication and Intelligent Systems. Algorithms for Intelligent Systems. Springer, Singapore. https://doi.org/10.1007/978-981-19-1324-2_5 , pages 31-43, May 2022.

Conference name: Third International Conference on Recent Trends in Communication and Intelligent Systems - ICRTCIS 2021

Link: https://link.springer.com/chapter/10.1007/978-981-19-1324-2_5

[6] Jyoti Pandey, Abhijit Asati and Meetha Shenoy, "Computational Operations and Hardware Resource Estimation in a Convolutional Neural Network Architecture. In: Roy, S., Sinwar, D., Perumal, T., Slowik, A., Tavares, J.M.R.S. (eds) Innovations in Computational Intelligence and Computer Vision . Advances in Intelligent Systems and Computing, vol 1424. Springer, Singapore. https://doi.org/10.1007/978-981-19-0475-2_17, Print ISBN: 978-981-19-0474-5, Impact Factor:0.63, SNIP:0.429, May 2022.

Conference name: ICICV-2021. Aug 05-06, 2021. (Online Mode). Received best paper award,

(Link: https://link.springer.com/chapter/10.1007/978-981-19-0475-2_17 )

[5] Prateek Sikka, Abhijit R Asati and Chandra Shekhar, "Low Area, High Throughput Field Programmable Gate Array Implementation of Microprocessor without Interlocked Pipeline Stages" In: Dhawan A., Tripathi V.S., Arya K.V., Naik K. (eds) Recent Trends in Electronics and Communication. Lecture Notes in Electrical Engineering, vol 777. Springer, Singapore. https://doi.org/10.1007/978-981-16-2761-3_58, December 2021. (Scopus Indexed Impact Score: 0.32 h-Index: 33 SJR: 0.134)

Conference name: VLSI, Communication and Signal Processing (VCAS 2020), Virtual Format, 9-11 October 2020.

(Link: https://link.springer.com/chapter/10.1007/978-981-16-2761-3_58 )

[4] Sunita Panda, Samiksha Sharma and Abhijit Asati, "Integrated Clock Gating Analysis of TG Based D Flip-Flop for Different Technology Nodes," In: Dhawan A., Tripathi V.S., Arya K.V., Naik K. (eds) Recent Trends in Electronics and Communication. Lecture Notes in Electrical Engineering, vol 777. Springer, Singapore. https://doi.org/10.1007/978-981-16-2761-3_9, December 2021. (Scopus Indexed Impact Score: 0.32 h-Index: 33 SJR: 0.134)

Conference name: VLSI, Communication and Signal Processing (VCAS 20202), Virtual Format, 9-11 October 2020. corresponding Author

(Link: https://link.springer.com/chapter/10.1007%2F978-981-16-2761-3_9 )

[3] Jyoti Pandey, Abhijit Asati and Meetha Shenoy, "A Novel Method for Suitable Hyper-Parameter Selection in an Accurate Convolutional Neural Network Architecture," Springer Lecture Notes on Networks and Systems), https://doi.org/10.1007/978-981-16-5120-5_39, Impact Factor: 0.17 h-Index: 14 SJR: 0.17, Vol. 288, B 513-E 526, Scopus-Indexed, Nov. 2021.

Conference name: 2^nd International Conference on Data Science and Applications (ICDSA 2021), School of mobile computing and communication, Jadhavpur university, Kolkata, India, April 10-11, 2021

( Link: https://link.springer.com/chapter/10.1007%2F978-981-16-5120-5_39 )

[2] Keshav. Raheja, Rohit Goel, and Abhijit Asati," An Improved DVFS Circuit & Error Correction Technique," In: Sharma H., Saraswat M., Yadav A., Kim J.H., Bansal J.C. (eds) Congress on Intelligent Systems. CIS 2020. Advances in Intelligent Systems and Computing, vol 1334. Springer, Singapore. Print ISBN: 978-981-33-6980-1, Online ISBN: 978-981-33-6981-8, https://doi.org/10.1007/978-981-33-6981-8_27, Impact Factor:0.63, SNIP:0.429, May 2021.

Conference name: Congress on Intelligent Systems (CIS 2020), World Conference Virtual Format, 4-6 , September, 2020. corresponding Author, presented paper

(Link: https://link.springer.com/chapter/10.1007/978-981-33-6981-8_27)

rticle/pii/S1877050915001222)

[1] Abhijit Asati and Chandra Shekhar, “ A purely MUX based high speed barrel shifter VLSI implementation using three different logic design styles,” Springer's Advances in Intelligent and Soft Computing, Vol. 125, pp. 639-646, December 2011 (ISBN: 978-3-642-27328-5, e-ISBN: 978-3-642-27329-2, DOI: 10.1007/978-3-642-27329-2, ISSN: 1867-5662) -- H index: 41, WOS, Scopus Indexed, Impact Factor:0.63, SNIP:0.429

Conference name: 3^rd International Asia Conference on Informatics in Control, Automation and Robotics (CAR 2011), Shenzhen, China, 24-25 December, 2011.

(Link: https://link.springer.com/chapter/10.1007/978-3-642-27329-2_88)

International Conferences in India (IEEE Explore and others)

[37] Jyoti Pandey, Abhijit Asati and Meetha Shenoy,"Convolutional Neural Network Hardware Optimization using Bayesian Method," Second IEEE and ACM Collaborative International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE'24) VIT, Vellore, February 2024 (Received Best Paper Award) (Available on IEEE Explore, DOI:10.1109/IC-ETITE58242.2024.10493483)

Link: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10493483

[36] Kartik Agrawal and Abhijit Asati,","Improved Implementation of PYNQ-Based FFT Hardware Accelerator,"2024 2nd IEEE International Conference on Device Intelligence, Computing and Communication Technologies (DICCT), March 2024.

[35] A. Senapati, M. Pareek and A. R. Asati, "Design and Analysis of a Scan Chain in Subthreshold Region," 2023 3rd International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON), Bangalore, India, 2023, pp. 1-6, (Available on IEEE Explore, doi: 10.1109/SMARTGENCON60755.2023.10442861).

Link: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10442861

[34] A. Kundu, N. K. Gupta and A. Asati, "Hardware Security of Scan Chain," 2023 IEEE 20th India Council International Conference (INDICON), Hyderabad, India, 2023, pp. 43-48, (Available on IEEE Explore,
doi: 10.1109/INDICON59947.2023.10440911).

Link: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10440911

[33] A. Harkishanka, A. Prakash, N. Gupta, A. Mohammad and A. Asati, "Hardware Software Co-design of k-means Clustering Algorithm," 2023 9th International Conference on Signal Processing and Communication (ICSC), NOIDA, India, 2023, pp. 688-693, (Available on IEEE Explore, doi: 10.1109/ICSC60394.2023.10441233)

Link: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10441233

[32] Jyoti Pandey, Abhijit R. Asati, Meetha V. Shenoy, Prateek Sikka, "Verification of Hardware Resource Utilization through High Level Synthesis for FPGA Implementation.," 4th Global Conference for Advancement in Technology - GCAT 2023, Bangalore. (Available on IEEE Explore, 10.1109/GCAT59970.2023.10353312)

(Link: https://ieeexplore.ieee.org/document/10353312 )

[31] Nidhi Arora, Akshay Sanadhya and Abhijit Asati, "Comparative Analysis of ST, ECRL and Static Logic Style at Different Process Technologies," Accepted in 2nd Series International Conference for Advancement in Technology ( 2nd ICONAT), 24-26 January 2023. (Available on IEEE Explore, DOI: 10.1109/ICONAT57137.2023.10080818)

corresponding Author

[Link: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10080818 ]

[30] Akshar Gandhi, Abhijit Asati,"A Low Voltage, Ultra-Low Power Subthreshold Bandgap Reference Circuit design with Transistor Stacking" 7th International Conference on Nanoelectronics, Circuits & Communication Systems (NCCS-2021) ISVE Ranchi. [will appear in Scopus Indexed Springer's Lecture Notes], corresponding Author

[29] Mohit Saini, Siddharth Shringi, Abhijit R. Asati, "An Improved Power Gating Technique with Data Retention and Clock Gating," Accepted in IEEE International Conference on Control, Automation, Power and Signal processing-CAPS 2021, IITDM Jabalpur, December, 10-12, 2021. (Available on IEEE Explore, DOI: 10.1109/CAPS52117.2021.9730489), corresponding Author

(Link: https://ieeexplore.ieee.org/document/9730489 )

[28] Prateek Sikka, Abhijit R Asati and Chandra Shekhar, "Area-optimal FPGA implementation of the YOLO v2 algorithm using High-Level Synthesis Low Area," IEEE 7^th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON), Prayagraj, India, 27-29 November 2020, pp. 1-6, Scopus Indexed (Available on IEEE explore, DOI: 10.1109/UPCON50219.2020.9376441)

(Link: https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9376441)

[27] Sunita Panda, Samiksha Sharma and Abhijit Asati, " Clock Gating Analysis of TG Based D Flip-Flop for Different Technology Nodes," IEEE 7^th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON), Prayagraj, India, 27-29 November 2020, pp. 1-6, Scopus Indexed (Available on IEEE explore, DOI: 10.1109/UPCON50219.2020.9376565), corresponding Author

(Link: https://ieeexplore.ieee.org/abstract/document/9376565)

(Link: https://link.springer.com/chapter/10.1007/978-981-33-6981-8_27)

[26] Prateek Sikka, Abhijit Asati and Chandra Shekhar, " High-Speed and Area-Efficient Sobel edge Detector on FPGA for Artificial Intelligence and Machine Learning Applications" International Conference on Automation, Signal Processing, Instrumentation and Control (ICASIC 2020), 27-28 February 2020, Vellore Institute of Technology, Vellore. Scopus Indexed

(Link: http://icasic2020.in/ https://onlinelibrary.wiley.com/doi/full/10.1111/coin.12334)

[25] Abhas Singh, Gurram Mahanth Kumar and Abhijit Asati, "Controller Architecture for Memory BIST Algorithms" IEEE International Conference on Electrical, Electronics and Computer Science, (SCEECS 2020), 22-23 February 2020, MANIT Bhopal. Scopus Indexed (Available on IEEE explore, DOI: 10.1109/SCEECS48394.2020.43, corresponding Author, presented paper)

(Link: https://ieeexplore.ieee.org/document/9087040)

[24] Priyesh Shukla, Abhijit Asati "Modular delay optimized mantissa multiplication architecture for 32-bit single precision floating point multiplier," 4th International Conference on Microelectronics, Circuits & Systems (Micro 2017), June, 3-4, 2017, Darjeeling, West Bengal, India (Indexed by Springer, corresponding Author)

(Link: https://micro2017.webs.com/publication)

[23] Garvit Goel, Gaurav Mittal and Abhijit R. Asati, "ROM based logic design for base-2 exponential and logarithm converter using fixed point number representation," IEEE International Conference on Inventive Computation Technologies (ICICT 2016), August 26-27, 2016, Coimbatore, Tamilnadu, India. -- H-index: 9, WOS and Scopus Indexed (available on IEEE explore, DOI: 10.1109/INVENTIVE.2016.7830227, corresponding Author)

(Link: https://ieeexplore.ieee.org/document/7830227)

[22] Vineet Kumar, Abhijit Asati, Anu Gupta,"Iris localization based on integro-differential operator for unconstrained infrared iris images," International Conference on Signal Processing, Computing and Control (ISPCC 2015), solan, Himachal Pradesh, India, 24-26 September 2015. H-index: 7, SNIP:0.448, WOS, Scopus Indexed, (available on IEEE explore, DOI: 10.1109/ISPCC.2015.7375040),

(Link: https://ieeexplore.ieee.org/document/7375040)

[21] Shrikant Bhutada, Abhijit Asati and Anuj Dubey "Design of ultra low power flip flops in sub-threshold region for bio-medical applications in 45nm, 32nm and 22nm technologies," The 2015 IEEE International Conference on Electrical, Computer and Communication Technologies (ICECCT 2015), 5-7, March, 2015, Coimbatore (India). --H-index: 11, SNIP:0.394, WOS and Scopus Indexed (available on IEEE explore, DOI: 10.1109/ICECCT.2015.7226146, corresponding Author)

(Link: https://ieeexplore.ieee.org/document/7226146)

[20] Priya Gupta, Divya Samnani, Anu Gupta, Abhijit Asati, "Design and ASIC implementation of column compression Wallace/Dadda multiplier in sub-threshold regime," Proceedings of the 9th INDIACom, 2nd International Conference on “Computing for Sustainable Global Development”, 11– 13 March, 2015, New Delhi. --H-index: 12, WOS and Scopus Indexed (available on IEEE explore)

(Link: https://ieeexplore.ieee.org/document/7100335)

[19] Priya Gupta, Anu Gupta and Abhijit Asati,"Power aware design of logarithmic prefix adders in sub-threshold regime: A comparative analysis," International Conference on Information and Communication Technologies (Under TEQIP Phase-II, ICICT 2014), 3-5 December 2014, Kochi. --Scopus Indexed (Elsevier Procedia Computer Science), H-index: 11

(Link: https://www.sciencedirect.com/science/article/pii/S1877050915001222)

[18] Priya Gupta, Ishan Munje, Nikhil Kaswan, Anu Gupta and Abhijit Asati, “Analysis & implementation of ultra low power 4-bit CLA in subthreshold regime,” IEEE International Conference on Circuit, Power and Computing Technologies” (ICCPCT 2014), 20-21 March 2014, Tamilnadu . --H-index: 6, WOS and Scopus Indexed (available on IEEE explore, DOI: 10.1109/ICCPCT.2014.7054765)

(Link: https://ieeexplore.ieee.org/document/7054765)

[17] Ashish Mishra, Abhijit Asati and Kota Solomon Raju, "Scheduling of dataflow graphs on partial reconfigurable hardware in Xilinx PR flow," International Conference on Advanced Electronic Systems (ICAES 2013), CEERI, Pilani, India. 21-23, September 2013. H-index: 7, Scopus Indexed, (available on IEEE explore, DOI: 10.1109/ICAES.2013.6659371, )

(Link: https://ieeexplore.ieee.org/document/6659371)

[16]Abhishek Mukherjee and Abhijit Asati, "Generic modified Baugh Wooley multiplier," International Conference on Circuits, Power and Computing Technologies (ICCPCT 2013), Kumaracoil (Tamilnadu), INDIA, 21-22 March 2013. H-index: 12, WOS and Scopus (available on IEEE explore, DOI: 10.1109/ICCPCT.2013.6529021, corresponding Author)

(Link: https://ieeexplore.ieee.org/document/6529021)

[15]Deepak Bharti and Abhijit Asati, "Design of a static current simulator using device matrix approach," International Symposium On Electronic System Design (ISED 2012), Kolkata, India, 19-22 December, 2012. H-index: 7, WOS and Scopus Indexed (available on IEEE explore, DOI: 10.1109/ISED.2012.38, corresponding Author)

(Link: https://ieeexplore.ieee.org/abstract/document/6526582)

[14]Ashish Mishra, Kritika Garg, Abhijit Asati and Soloman Raju, "Hardware software codesign using profiling and clustering," IEEE International Conference on Communication, Information and Computing Technology (ICCICT 2012), Mumbai, India, 19-20 October 2012. H-index: 7, Scopus Indexed (available on IEEE explore, DOI: 10.1109/ICCICT.2012.6398118)

(Link: https://ieeexplore.ieee.org/document/6398118)

[13]Deepak Bharti and Abhijit Asati, "Device matrix algorithm: A new semiconductor modeling approach for plotting band structures," International Conference on Materials Science and Technology (ICMST 2012), Kottayam, India, 10-14 June, 2012. (IOP conference series, corresponding Author)

(Link: http://www.icmst2012.com/)

[12] Deepak Bharti and Abhijit Asati, "A Novel multi-planar band structure algorithm: Planar region matrix approach," International Conference on MATLAB Applications in Engineering and technology (ICMAET 2012), Bangalore (India), 1-2 January 2012. (Best Paper Award), (available online in the Elsevier Digital Commons Platform , ISBN: 978-93-81693-12-4)

(Link: https://www.interscience.in/conf_proc_volumes/34/)

Scopus Indexed (available on IEEE explore, corresponding Author)

[11] Deepak Bharti and Abhijit Asati,"3-D device matrix approach: A new algorithm for plotting energy band diagrams in semiconductors," IEEE Students' Conference on Electrical, Electronics and Computer Sciences (SCEECS 2012), Bhopal, India, 1-2 March 2012. DOI: 10.1109/SCEECS.2012.6184800, H-index: 11, corresponding Author)

(Link: https://ieeexplore.ieee.org/document/6184800)

[10] Abhijit Asati and Dr. Chandra Shekhar, "A fully pipelined 8×8 Baugh Wooley multiplier design using modified TSPC logic design style," COMMUNE, International Conference on Advancements in Communication & Computing Systems (CACCS 2012), Gr. NOIDA,UP, India, 24-25 March 2012.

(Link: https://scholar.google.com/citations?view_op=view_citation&hl=en&user=h_dycmkAAAAJ&cstart=20&pagesize=80&citation_for_view=h_dycmkAAAAJ:IjCSPb-OGe4C)

[9] Abhijit Asati and Dr. Chandra Shekhar, "A 16*16 Baugh Wooley multiplier design using optimized static CMOS logic style," International Conference On Communication, Computation and Nanotechnology (ICN 2010), Bhalki, India, 29-30 October, 2010.

[8] Abhijit Asati and Dr. Chandra Shekhar, "A purely MUX based high speed barrel shifter design," International conference on Advances in Computer Vision and Information Technology, (ACVIT 09), Aurangabad, India, 16-19 December 2009. (Book chapter in Computer vision and information technology : advances and applications ; I.K. Internat. Publ. House 2010, New Delhi, ISBN:9789380026954 9380026951, OCLC Number: 845904182)

Link:

https://www.worldcat.org/title/computer-vision-and-information-technology-advances-and-applications/oclc/657271024&referer=brief_results

[7] Abhijit Asati, S.K.Sahoo and Dr. Chandra Shekhar, "Selection of optimum device size and trans-conductance ratio for high speed digital CMOS inverter design for a given fan out load," IEEE International Conference On Emerging Trends In Engineering and Technology, (ICETET 09), Nagpur, India, 16-18 December, 2009. DOI: 10.1109/ICETET.2009.199, H-index: 14, SNIP:0.352, WOS, Scopus Indexed (available on IEEE explore, corresponding Author, presented paper)

(Link: https://ieeexplore.ieee.org/document/5395495)

[6] Vivek Gupta, Anu Gupta, Nitin Chaturvedi, Abhijit Asati, “A novel technique for improvement of power supply rejection ratio in amplifier circuits, ” International Conference on Advances in Computing, Control & Telecommunication Technologies, (ACT 2009), Trivandrum, India, 28-29 December, 2009. DOI: 10.1109/ACT.2009.191, Scopus Indexed (available on IEEE explore), H-index: 16

(Link: https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5375827)

[5] Abhijit Asati and Chandra Shekhar, “Digital CMOS high-speed level shifter design,” International Conference on VLSI and Communication (ICVCom 2009), Saintgits College of Engineering, Kottayam, India, 16-18 April, 2009 .

(Link: http://www.allconferences.com/conferences/2008/20081103021442 )

[4] Abhijit Asati and Chandra Shekhar, “A high-Speed hierarchical, 16*16 array of array multiplier design,” IEEE, International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT 2009), A.M.U. Aligarh, India, 14-16 March, 2009.DOI: 10.1109/MSPCT.2009.5164200, H-index: 8, WOS, Scopus Indexed (available on IEEE explore, corresponding Author, presented paper)

(Link: https://ieeexplore.ieee.org/document/5164200)

[3] Abhijit Asati and Chandra Shekhar, “An improved high speed fully pipelined 500 MHz 8´8 Baugh-Wooley multiplier design using 0.6 um CMOS TSPC logic design style,” IEEE Region 10 Colloquium and 3rd International Conference on Industrial and Information Systems (ICIIS 2008), IIT Kharagpur, India, 8-10 December, 2008. DOI: 10.1109/ICIINFS.2008.4798406, H-index: 12, WOS, Scopus Indexed,, available on IEEE explore, WOS, corresponding Author, presented paper)

(Link: https://ieeexplore.ieee.org/document/4798406)

[2] Abhijit Asati and Chandra Shekhar, “An optimized approach for a CISC microprocessor design using micro coded controller technique,” International Conference on Wireless and Embedded systems (WECON 2008) Rajpura, India, 18-19 October, 2008.

(Link: https://www.chitkara.edu.in/wecon/wecon-2008.php)

[1] S.K.Sahoo, Abhijit Asati, Rasmitha Sahoo and Dr. Chandra Shekhar, “A high speed radix-64 Parallel Multiplier Using a Novel Hardware Implementation approach for partial product generation based on redundant binary arithmetic,” IEEE International Conference On Emerging Trends In Engineering and Technology (ICETET 08), Nagpur, India, 16-18 July, 2008. DOI: 10.1109/ICETET.2008.128, H-index: 19, Scopus Indexed (available on IEEE explore, presented paper)

(Link: https://ieeexplore.ieee.org/document/4579947)

Conference Tutorials

[1] Sikka Prateek, Abhijit Asati, Chandra Shekhar. “Novel methods for Area, Speed and Power optimization using HLS for FPGA prototyping.” IEEE UPCON, 2020 MNNIT Allahabad

National Conferences and Workshops

[7] Abhinav Bhansali, Abhijit Asati, ”Optimizing the ratio of number of tubes in PCNTFET to NCNTFET for digital circuits,” “Technology-Innovation, (TECHNOVATION) 2-4 February, 2018, Jaipur.

[6] Priya Gupta, Anu Gupta and Abhijit Asati "Leakage immune 9T-SRAM cell in sub-threshold region" National Conference On Advances in Microelectronics, Instrumentation and Communication (MICOM), November 2015, BITS, Pilani.

(Link: http://www.bits-pilani.ac.in/microadmin/login.aspx )

[5] Attended two days STM 32 training program at ST Microelectronics, Greater Noida on Oct 10-11, 2012.

[4] Attended 'University Day' program at ST Microelectronics, Greater Noida on Nov 16, 2010.

[3] Delivered a talk on “Design of Barrel Shifter” High performance Digital System Design workshop at BITS, Pilani, 16-18 January, 2009.

[2] Delivered a talk on “Design of Barrel Shifter” High performance Digital System Design workshop at BITS, Pilani, 16-18 January, 2009.

[1] Attended 4-days Workshop on “Elements of Microelectronics” jointly organized by INTEL Higher Education and IIT Bombay, between 17-20 December, 2003.

BITS Pilani

Publications and Projects

Patent, Projects, Journals, Conferences and talks

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